The present invention relates to a computer-aided LSI design technique. It more specifically pertains to a method for estimating the wire length and area of an actual layout before performing a layout design, with a view to achieving a reduction of the number of LSI design steps.
Recent remarkable developments in technology of reducing the dimensions of LSI have accomplished very large-scale integration which makes it possible to fabricate very large-scale integrated circuits (VLSIs) at the level of millions of gates. Meanwhile, electronic devices, such as multimedia equipment, have been improved in performance as well as in weight. Therefore, technology capable of providing one-chip large-scale integration is in great demand. Various top-down design techniques have been proposed to design and develop high-performance VLSIs. In a top-down design technique, LSI functional specifications are specified by languages and subsequent design steps up to the generation of logical circuits are carried out automatically by computer. The amount of data dealt with in each design step is increased in the order of language design level, logical circuit design level, and layout design level. Therefore, the efficiency of development can be improved as a whole by laying out a design at the level of language.
In conventional LSIs, the wire delay is less than the macrocell delay and the signal delay, which seriously affects circuit timing specifications, is almost determined by macrocell driving performance. Accordingly, it is possible to design LSIs by performing logical synthesis with the aid of an automatic synthesis system (e.g., Design Analyzer manufactured by Synopsys) having the function to take into account timing specifications.
However, as the dimensions and integration of LSI is improved, the ratio of the wire delay to the circuit delay increases. In performing a logical synthesis process according to top-down design technology, it becomes necessary to take into account a wire delay that has been ignored. That is, both the wire resistance and the capacitance between wires relatively increase with respect to the transistor drive performance, and performing a design without taking wire delay into account will give rise to an inconvenient circumstance that it becomes necessary to repeat a logic synthesis process after a layout design is completed. This produces a bar to improvements in the design efficiency.
As can be seen from the above, it is necessary to take into account layout results, particularly wire length and layout area, in a logical synthesis process. For this reason, there have been strong demands for a fast and accurate estimating method for estimating layout results.
Typical techniques of estimating layout results are shown below.
(a) A layout result estimation is formed by layout result statistical processing. PA1 (b) A layout result estimation is formed by actually performing either rough placement or rough wiring. PA1 (c) A layout result estimation is formed from circuit characteristics on the basis of a netlist. PA1 (a) an information extracting step of extracting, from said netllst and said cell library, information including the total number of nets, the number of nets for each fan-out, and the types and areas of cells belonging in each net, for an estimation-target block in said LSI; PA1 (b) a basic wire length determining step of determining, based on said information extracted in said information extracting step, a net basic wire length for each fan-out as a reference to wire length estimation; and PA1 (c) a net wire length estimating step of estimating, based on said information extracted in said information extracting step, a net wire length for each fan-out by making reference to said net basic wire length for said fan-out determined in said basic wire length determining step and taking into account net expansion due to the distribution of cells in a cell placement; PA1 wherein the total wire length of said estimation-target block is estimated based on said estimated net wire lengths. PA1 (a) a wire length estimating step of estimating the wire length of an estimation-target block in said LSI; PA1 (b) a wiring area estimating step of estimating, from said wire length estimated in said wire length estimating step, a wiring area of a layout occupied by wires; and PA1 (c) a layout area estimating step of estimating, from said wiring area found in said wiring area estimating step and the total cell area and over-the-cell wiring utilization area of said estimation-target block, the layout area of said estimation-target block; PA1 wherein said layout area estimating step determines said total cell area to be the layout area of said estimation-target block when said wiring area is smaller than said over-the-cell wiring utilization area and obtains, when said wiring area is greater than said over-the-cell wiring utilization area, said estimation-target block's layout area from a difference between said wiring area and said over-the-cell wiring utilization area and from said total cell area PA1 (a) an information extracting step of extracting, from said netlist and said cell library, information including the total number of nets, the number of nets for each fan-out, and the types and areas of cells belonging in each net, for said estimation-target block; PA1 (b) a basic wire length determining step of determining, based on said information extracted in said information extracting step, a basic wire length for each fan-out as a reference to wire length estimation; and PA1 (c) a net wire length estimating step of estimating, based on said information extracted in said information extracting step, a net wire length for each fan-out by making reference to said net basic wire length for said fan-out determined in said basic wire length determining step and taking into account net expansion due to the distribution of cells in a cell placement; PA1 wherein the total wire length of said estimation-target block is estimated based on said estimated net wire lengths.
In the method (a), it is impossible to reflect the versatility of circuit and, as a result, wire length estimation, inclusive of redundancy containing circuit variations, is required. It becomes difficult to lay out an optimal design both in the aspect of area and in the aspect of performance. In the method (b), either a rough placement process or a rough wiring process is carried out, which makes it possible to obtain an estimated result corresponding to circuit characteristic. However, the method (b) is a very time-consuming technique. A considerable reduction of the design period may not be expected.
The remaining method (c) has the ability to improve the efficiency of design. Various techniques, based on the number of cell instances and the number of nets as to a netlist, have been proposed.
C. Sechen shows, in "Average Interconnection Length Estimation for Random And Optimized Placements," In Proc. of ICCAD, pp. 190-193, 1988, an estimating method. In this estimating method, a checkerboard model, in which square cells having an average area are laid out in 2-D square grid form, is used in order to estimate the length of wiring when net terminals are distributed in random manner by means of combinational computing. Massoud Pedram and Bryan Preas show, in "Interconnection Length Estimation for Optimized Standard Cell Layout," In Proc. of ICCAD, pp. 390-393, 1989, a method for forming an estimation of the length of wiring by finding a distribution of terminals within a multi-terminaled bounding box.
Takeo Hamada and others show, in "A Wire Length Estimation Technique Utilizing Neighborhood Density Equations." In Proc. of 32nd Design Automation Conference, pp. 402-407, 1995, a method for forming an estimation of the length of wiring by expressing the neighborhood relationship of cells belonging in a netlist with neighborhood density equations.